Backside illuminated image sensors have been developed since 1973[1], shortly after the invention of the CCD. Until a few years ago, this was limited to charge-coupled devices for high-end applications. Recently, several developments on CMOS image sensors with backside illumination were started, driven by the scaling for small pixels in consumer image sensor applications. In all of these applications, a fully processed wafer of image sensors is thinned through a mechanical and/or chemical thinning process. Before thinning, the wafer is attached to a mechanical handle wafer. Then a mechanical grinding followed by a chemical etching step is used to thin the wafer. Thicknesses of the wafer down to 3 or 5 micron have been used. The sensor is then illuminated from the backside.
A problem that occurs after thinning is the passivation of the backside surface of the image sensor. Without any special measures, a native silicon oxide layer (SiO2) will be formed at the surface of the silicon. The interface between the silicon and the SiO2 layer contains defects in the silicon surface (dangling bonds), which form generation centers of free electrons. Without any specific measures, these free electrons will diffuse into the p-epitaxial layer of the detector and get collected by the photodiode. The generation of these electrons is thermally activated. This will create a significant contribution to the dark current of the image sensor, which is dominant if no countermeasures are taken. Counter measures have to be taken that allow that these charges recombine before they diffuse into the substrate. The silicon oxide layer also contains a fixed density of positive charges. Without passivation implant, an inversion layer will be formed at the surface. Photoelectrically generated charges in the substrate can be trapped at this surface due to this electric field (see FIG. 1). This can cause history effects on the sensor, since the amount of trapped charges may vary over time. This is another reason why a surface passivation is required.
In order to reduce these effects, a native oxide layer is usually avoided and the surface is passivated by an implant (see FIG. 2). In first place, a pre-formed thermally grown SiO2 layer is present. This layer can be present upfront, as is the case in thinning of image sensors processed on silicon-on-isolator substrates [2,3,4] or it can be deposited in a bulk silicon process [5]. To effectively passivate the surface, three approaches are followed.
1) With SOI substrates, a highly doped p+ layer is deposited close to the SOI substrate. This layer is already present in the SOI start material before the CMOS or CCD device processing [2,3,4];
2) with bulk silicon wafers, after the thinning process, the wafers receive a backside p+ implantation followed by a laser anneal to activate the implant [5];
3) with MBE (Molecular Beam Epitaxy), an atomic layer with very high boron concentration is deposited creating a very sharp delta function in the doping. This technique is known as delta doping [6].
Traditionally, delta doping has been the only satisfactory method that can realize a good UV sensitivity due to the very shallow thickness of the passivation implant (which is only a few atomic layers thick). The other methods result in a p+ highly doped layer in the first 10-100 nm of the silicon. Photocharges generated in this layer have a high probability to recombine. This reduces the sensitivity of the image sensor for short wavelengths (in the UV wavelength range between 200 and 400 nm).
References [8], [9] describe image sensors processed on Silicon on Sapphire (SOS) substrates. The carrier wafer is a thick sapphire wafer (typically 725 μm thick) on which a thin (5 μm) layer of silicon is deposited. Sapphire is used because of its transparent properties, allowing the sapphire substrate to remain after processing while still allowing the image sensor to be illuminated from the backside through the sapphire wafer.